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WiFi模块常用通讯接口

发布日期:2017-01-05 浏览次数:3437
WiFi模块常用通讯接口包含:USBSDIOSPIslave)、UARTRGMIIRMIISKYLAB WiFi模块常用的通讯接口如下:(点击型号进入相关模块页)

USB: WG209 ,WG203,WG211

SDIO: WG213 (研发中)

UART: WU105, WU106

GMII: SKW78

MII: SKW71,SKW72,SKW73,SKW75,SKW92A/B,SKW77

以下是这些接口的信号PIN脚定义(不包含电源)

USB

信号名称

类别

描述

USB_DPOS

IA/OA

USB D+ signal, carries USB data to and from the USB2.0 PHY

USB_DNEG

IA/OA

USB D- signal, carries USB data to and from the USB2.0 PHY

SDIO

信号名称

类别

描述

SDIO_CLK

I

SDIO input clock from host

SDIO_CMD

I/O

SDIO command line

SDIO_DATA0

I/O

SDIO data line

SDIO_DATA1

I/O

SDIO data line

SDIO_DATA2

I/O

SDIO data line

SDIO_DATA3

I/O

SDIO data line

SPI(Slave)

信号名称

类别

描述

SPI_CLK

I

SPI serial interface clock

SPI_CS_L

I

SPI chip select

SPI_INTR_L

O

SPI interrupt

SPI_MISO

O

Data transmission from the module to an external device

SPI_MOSI

I

Data transmission from an external device to the module

UART

信号名称

类别

描述

UART_CTS

I

UART clear to send signal

UART_RTS

O

UART ready to send signal

UART_RXD

I

UART receive data

UART_TXD

O

UART transmit data

RGMII

信号名称

类别

描述

RGMII_TX_CLK

O

Transmit clock

RGMII_TX_CTL

O

Transmit control

RGMII_TX_DATA0

O

Transmit data

RGMII_TX_DATA1

O

Transmit data

RGMII_TX_DATA2

O

Transmit data

RGMII_TX_DATA3

O

Transmit data

RGMII_RX_CLK

I

Receive clock

RGMII_RX_CTL

I

Receive control

RGMII_RX_DATA0

I

Receive data

RGMII_RX_DATA1

I

Receive data

RGMII_RX_DATA2

I

Receive data

RGMII_RX_DATA3

I

Receive data

RGMII_MDIO

I/O

Management control interface data

RGMII_MDC

O

Management control interface clock

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